1. Field of the Invention
The present invention relates to electrical and electronic circuits and systems. More specifically, the present invention relates to systems and methods for improving single event upset performance of digital circuits.
2. Description of the Related Art
Particulate radiation (such as energetic electrons, protons, or ions) in space and airborne environments can cause errors (upsets) to occur in digital circuits. The response to an energetic particle is a transient pulse disturbing the voltage of one or more nodes. This may cause a logic level to change state to an opposite value for a time t. The duration t is technology dependent; for a given technology and particle energy spectrum, there is a distribution of t. If the duration t is greater than a threshold value, subsequent logic in the circuit will be responsive to it, causing errors.
If the perturbation occurs on a node within a storage element (or on its clock), its value could be switched. This is a storage element single event upset (SEU). If the perturbation occurs in combinational logic, it is a single event transient (SET). If the SET propagates to a storage element and appears at the time of sampling, than an SEU also occurs. The probability of this occurring is dependent on the clock frequency. If the SET is not captured by a storage element, then it disappears with no effect.
Upset is an increasing problem in space (and even critical terrestrial) applications, since evolving digital technologies are of ever-smaller features sizes and smaller feature-sized technology is more susceptible to upset by radiation. In order to use these technologies, methods must be provided to mitigate upset.
Conventional solutions use changes in the semiconductor process and/or internal circuit design to provide upset resistance. One standard approach is to design cells such that the transient pulse amplitude and/or, response are reduced. This, however, results in a larger cell size that can decrease the logic density by a factor of two to four. In addition, the logic may become slower by a factor of two or more. An alternate approach involves design modification of the storage elements by using techniques to filter transients in the internal holding loop of the latch (the core of a storage element). This approach, however, increases the size of the latch by a factor of two to three. It is also difficult to control the delays used in this system, resulting in the use of delays that are two to three times greater than the amount required by the system design.
In addition to reduced system performance (larger size, slower speed), prior approaches are also typically fixed and immutable, once designed. Since systems are usually designed to accommodate the worst-case process variations and the worst-case radiation environment, they typically carry a performance penalty that is greater than necessary.
Hence, a need exists in the art for an improved system or method for making digital circuits resistant to single event upset that offers reduced circuit size, improved performance, and greater flexibility than prior approaches.